Researchers on the Automation, Verification and Security (AVS) Lab on the Indian Institute of Technology (IIT) Guwahati, has developed safe and reliable built-in circuits (ICs) for sooner and environment friendly computing.
The analysis appears in any respect features of the automated electronics design course of like synthesis, verification and safety, and contributes in the direction of strengthening the electronics manufacturing ecosystem in our nation.
“A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks,” Chandan Karfa, affiliate professor, Department of Computer Science and Engineering, IIT Guwahati stated.
IIT Guwahati workforce has emphasised on {hardware} acceleration specs which might be usually written in high-level languages like in C/C++ and are transformed to {hardware} code (or register switch stage or Register−Transfer Level (RTL code), in a course of known as High-Level Synthesis (HLS). Due to the complicated dialog course of, HLS translation could introduce bugs within the design and due to this fact stringent validation steps are required. The RTL simulators are used to validate HLS, however these are sluggish and sophisticated. The workforce has developed easy and quick instruments for HLS validation.
“We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features,” Karfa added.
In addition to those simulators, prototypes of which can be found for testing, the IIT Guwahati workforce has additionally developed a expertise known as HOST, which protects Integrated Circuits from IP theft throughout the design cycle. has been proven to be resilient to any recognized assault until date.
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Source: www.financialexpress.com”